This invention relates generally to operational amplifiers and in particular to CMOS operational amplifiers, and is more particularly directed toward small geometry CMOS operational amplifier architectures suitable for implementation in deep sub-micron processes.
An op amp (operational amplifier) architecture is desirable which is suited to current and foreseeable future generations of small geometry CMOS (complementary metal-oxide-semiconductor), manufactured economically in high volume for digital circuitry. Modern deep sub-micron (DSM) processes have gate lengths much less than one micron. DSM scaling also requires scaling the gate oxide thickness which requires scaling the supply voltage: for example, from 0.6 xcexcm (microns) at 5 volts down to 0.13 xcexcm at 1.0 volt.
The conventional op amp, illustrated in FIG. 1 in block diagram form, and generally depicted by the numeral 100, comprises two gain stages. The first functions as a differential transconductance (gm) stage 101 and the second as an integrator 103, separated by a differential to single-ended converter 102. The conventional op amp 100 is illustrated in more detail in FIG. 2.
As shown in FIG. 2, the gm stage 101 comprises a differential pair 201, 202 with a single current source xe2x80x9ctailxe2x80x9d 203 (both typically, and as an example, n-type insulated-gate field effect transistors), and two current source loads 204, 205 (typically, and as an example, provided by p-type transistors). By selecting an output 206 from only one of the differential input stages, differential to single-ended conversion is accomplished.
This single-ended output 206 is then applied to the integrator stage 103. In the implementation shown, the integrator 103 includes a p-type output transistor 207 with a current source tail 210, and Miller capacitor 208. A nulling resistor 209 has been added for the sake of stability. This configuration requires the negative supply to exceed the most negative input signal voltage by one Vt plus one saturation voltage, and the positive supply to exceed the most positive input signal voltage by one saturation voltage less one Vt. Vt is the threshold voltage of the MOS transistors 201, 202 above which conduction occurs.
In the conventional op amp implementation, the integrator comprises an inverter and Miller capacitor. In DSM CMOS, the gain of a simple inverter is low, so it is usually necessary to cascode both active devices. The supply voltage in total must therefore exceed the maximum signal swing by four saturation voltages. Consequently, this architecture is difficult to implement where the supply voltage is constrained by DSM processing.
The DSM CMOS technology also suffers from DC and low frequency mismatching and noise, resulting in the amplifier described above having poor offsets and noise performance. To condition signals from a high impedance source it is desirable to have an op amp with a low voltage offset (Vos) and low input bias current (Ib). Op amps with bipolar input devices, especially laser trimmed, have a low Vos but high Ib. Op amps having JFET (junction field-effect transistor) input devices, even if laser trimmed, have a low Ib but high Vos, while op amps using CMOS input devices, as noted above, have lower Ib but higher and less stable Vos than JFET or bipolar op amps. Bipolar and JFET technologies, especially when laser trimmed, are expensive and incompatible with low cost digital circuitry.
It is known in the art that these shortcomings may be reduced by chopping the gm stage. This is conventionally done at a low frequency, for example 10 kHz, and such amplifiers are generally used only with low bandwidth signals. Chopping may be viewed as modulating the input signal up to an amplitude modulation of a carrier frequency, amplifying the AC (alternating current) signal at the carrier frequency, and demodulating it back to a DC (direct current) signal. The demodulated signal then contains the DC offset of the amplifier modulated up to an amplitude modulation of the carrier frequency, which must subsequently be removed by filtering. At a low carrier frequency, this filtering requires large components that are difficult to integrate and that limit the signal bandwidth.
An improved chopping technique provides for greater signal bandwidth by having two amplifiers. The low frequency and high frequency components of the signal are separated; the LF (low frequency) component may be amplified by a LF chopped CMOS op amp with low Vos and low Ib, while the HF (high frequency) component may be amplified by a parallel wide-band amplifier. The two components are then recombined. However, this approach requires two amplifiers and still requires large low-frequency filtering components.
An alternative approach is to use a single chopped CMOS op amp with an increased modulation frequency on the order of many megahertz. A disadvantage of this approach is that the modulating switches must be made relatively large, and, due to inevitable manufacturing tolerances and resultant dimensional mismatches, these switches induce a large offset voltage and input bias current, partly nullifying the original purpose of the design.
Consequently, a need arises for an op amp with a low Vos and low Ib that may be manufactured using low-cost digital-compatible CMOS technology.
These needs and others are addressed by the improved CMOS op amp of the present invention, which, in one embodiment, provides a chopped CMOS op amp implemented in a deep sub-micron process. The input signal is modulated to an amplitude modulation on a high frequency carrier, where the carrier frequency may, for example, be 100 MHz. The modulator preferably comprises CMOS switches, which function as intended even when the signal swing is rail-to-rail. After modulation, the signal is AC, and may thus be capacitively coupled (with small integrated capacitors due to the high modulation frequency) and level shifted to any convenient DC level.
The differential input stage (gm stage) may be implemented with simple inverters with any supply voltage exceeding just two saturation voltages plus only a small allowance for the small AC voltage excursion. This gm stage may be implemented with a single inverter, although a higher gm (and thus enhanced slew rate and reduced distortion) may be obtained by having two inverters: the first functions as a voltage gain stage, whose gain multiplies up the gm of the second stage. To maintain overall loop stability, the propagation delay through this voltage gain stage must be very low; however, this stage must be operated at high current levels to achieve low input thermal noise, and it will thus naturally have low delay.
Amplifying the signal as an AC modulation has the further advantage that DC offsets and low frequency noise in the amplifying devices, characteristic of DSM CMOS, are removed at the demodulator. The primary source of offsets and associated low frequency noise are then the modulating switches. These offsets are, in a practical implementation, already lower than would be obtained by DC amplification in DSM CMOS.
Advantages of using a modulation frequency that is as high as the technology permits (e.g., 100 MHz in 0.35 xcexcm 3.3 v technology) are that AC coupling and filtering of the AC signal may be performed by small on-chip components, and the input signal frequency may be as high as 1 MHz, for example.
To accomplish this, the integrator is implemented with inverters which are not cascoded, and the required gain, matching or indeed exceeding that which may be achieved with one cascoded inverter (as would be conventional), is achieved by using three inverters. Such an integrator is inherently unstable: it forms a ring oscillator. It is therefore stabilized by nesting a second compensation capacitor within the outer ring of the integrator, with a Miller capacitor around the second inverter. This configuration is stable.
This architecture is suited for integrated implementation in DSM CMOS while retaining a combination of useful signal amplitude, high overall DC gain, and low input offsets, along with low noise and useful signal bandwidth.
As noted, however, improving amplifier performance by chopping can result in undesired effects. The principal undesired effects are the appearance of a low-frequency square wave at the amplifier output, and charge feedback from the switches into the signal source, particularly due to charge flow imbalance. In accordance with another embodiment of the present invention, an op amp is implemented using a deep-sub-micron low-voltage CMOS technology, where traditional offset reduction techniques (bipolar input devices, laser trimming, etc.) are not available. As noted above, it is known that the input offset voltage of an op amp with a differential mode input stage can be reduced by chopping; that is, periodically reversing the complementary input and output connections of the differential stage.
As explained previously, this chopping process may be viewed as modulating the DC input signal to an AC signal at the switching frequency, amplifying it as an AC signal, and then demodulating it back to a DC signal. Offsets later in the signal path may cause DC offsets, but these are attenuated in closed-loop by the gain of the preceding stages. Ideally, this results in near-zero input DC offset, provided that the modulating switches are perfectly symmetric, particularly in their charge injection due to feedthrough of the switching clocks. Of course, perfect symmetry is not achievable in practice.
The present invention substantially compensates for the high Vos and Ib induced by large, mismatched modulating switches, working at a high modulation frequency on the order of 100 MHz, to result in an op amp with relatively low Vos and Ib that is fully integratable in a low-cost manufacturing technology compatible with digital circuitry, and further provides a relatively broad signal bandwidth.
For example, in a 0.35 xcexcm 3.3 volt CMOS technology, it is possible to make an op amp with a Vos of less than 100 xcexcV (microvolts), Ib less than 5 nA (nanoamperes) and THD (total harmonic distortion) of less than xe2x88x9272 dB (decibels) when used as an amplifying buffer with a useful signal bandwidth of 500 kHz. This combination of specifications is difficult to achieve with other known techniques. The high DC precision CMOS op amp of the present invention exhibits values of Vos and Ib that are improved by an order of magnitude over an equivalent high frequency chopped CMOS op amp of the prior art.
In accordance with one aspect of the invention, an improved chopped CMOS operational amplifier is provided that includes a modulator having differential input and output connections, an AC amplifier coupled to the modulator output, a demodulator coupled to the AC amplifier output, and an integrator coupled to the demodulator output. The improvement is realized in that the operational amplifier has a gain path comprising at least four inverting amplifiers, wherein three or a greater odd number of the inverting amplifiers comprise an integrator that is rendered stable by incorporating a nested integrating capacitor within the integrator, and at least one of the inverting amplifiers is coupled to the modulator output and configured as the AC amplifier. Preferably, the modulator and demodulator operate at a clock frequency of at least 50 MHz.
In accordance with one aspect of the invention, first clock signals are coupled to the modulator and demodulator, wherein the demodulator comprises a first demodulator, and a second demodulator is coupled to the AC amplifier output, wherein the second demodulator is operated by second clock signals. A compensating signal is derived from the second demodulator, the compensating signal attenuating input offset voltage components attributable to modulator switch mismatch. The compensating signal derived from the second demodulator acts to adjust at least one characteristic of the first clock signals, which may be an amplitude characteristic. In a preferred form of the invention, the compensating signal derived from the second demodulator is inserted into the primary signal path. The compensating signal comprises first clock signals, and the compensating signal is inserted into the primary signal path by operating the modulator and first demodulator with first clock signals.
In accordance with one aspect of the invention, the first clock signals comprise an ensemble of four amplitude-adjusted clock signals, wherein two of the amplitude-adjusted clock signals are derived from a first system clock phase, and two of the amplitude-adjusted clock signals are derived from a second system clock phase. The first system clock phase is in antiphase with respect to the second system clock phase.
In another form of the invention, the second clock signals are orthogonal with respect to the first clock signals. Both the first clock signals and the second clock signals may comprise a pair of antiphase clock signals, where each one of the second clock signals is orthogonal with respect to each one of the first clock signals.
In still another form of the invention, the compensating signal is derived from the second demodulator by operating the second demodulator with second clock signals that are orthogonal with respect to the first clock signals. Preferably, the compensating signal is derived by remodulating output signals from the second demodulator and reinserting the remodulated signals into the main signal path. The remodulated signals are reinserted into the main signal path by capacitive coupling.
In accordance with still another aspect of the improved chopped CMOS operational amplifier of the present invention, the modulator and demodulator are operated by first clock signals, and an interface network is coupled between the modulator and the AC amplifier, wherein the interface network interrupts the gain path during transitions of the first clock signals. Preferably, the interface network comprises a pair of transistor switches operated by clock signals comprising sequences of relatively narrow pulses substantially centered around the state transitions of the first clock signals, such that each transistor of the pair of transistors is ON when first clock signals are in a steady state, and OFF when first clock signals are changing state.
In a preferred form of the invention, the modulator comprises an arrangement of transistor switches that reconfigures input-to-output connections at the clock rate. This arrangement of transistor switches couples a first input of the modulator to a first output, and a second input of the modulator to a second output, during a first clock phase, then couples the first input to the second output and the second input to the first output during a second clock phase. The first demodulator, on the other hand, reverses the input-to-output reconfiguration introduced by the first modulator.
In accordance with still another aspect of the invention, the first demodulator includes first and second outputs, with a current inverter coupled to one of the outputs to perform differential to single-ended conversion. In an alternative form, the first demodulator may comprise two capacitors per channel, with an associated network of clock-driven MOS transistor switches that enable each of the capacitors to transmit channel current in a first configuration, store channel current in a second configuration, and discharge stored channel current in a third configuration, to accomplish demodulation and differential to single-ended conversion.
In accordance with yet another embodiment of the present invention, a chopped CMOS operational amplifier comprises a primary signal path including an AC amplifier preceded by a first modulator and followed by a first demodulator, wherein the modulator and demodulator are operated by first clock signals, and a second demodulator coupled to the AC amplifier output, the second demodulator operated by second clock signals, wherein a compensating signal is derived from the second demodulator, the compensating signal attenuating input offset voltage components attributable to modulator switch mismatch. Preferably, the compensating signal derived from the second demodulator acts to adjust at least one characteristic of the first clock signals. This characteristic may be an amplitude characteristic of at least one of the first clock signals. The compensating signal derived from the second demodulator is inserted into the primary signal path.
In one form of the invention, the compensating signal is inserted into the primary signal path by operating the modulator and first demodulator with first clock signals. Preferably, the first clock signals comprise an ensemble of four amplitude-adjusted clock signals, wherein two of the amplitude-adjusted clock signals are derived from a first system clock phase, and two of the amplitude-adjusted clock signals are derived from a second system clock phase. The first system clock phase is in antiphase with respect to the second system clock phase.
In accordance with still another form of the invention, the second clock signals are orthogonal with respect to the first clock signals. Both the first clock signals and the second clock signals comprise a pair of antiphase clock signals, wherein each one of the second clock signals is orthogonal with respect to each one of the first clock signals.
The compensating signal may be derived from the second demodulator by operating the second demodulator with second clock signals that are orthogonal with respect to the first clock signals. In one form of the invention, the compensating signal is derived by remodulating output signals from the second demodulator and reinserting the remodulated signals into the main signal path. In a preferred form, the remodulated signals are reinserted into the main signal path by capacitive coupling.
In accordance with still a further form of the invention, the modulator and demodulator are operated by first clock signals, and an interface network is coupled between the modulator and the AC amplifier, wherein the interface network interrupts the gain path during transitions of the first clock signals. The interface network may comprise a pair of transistor switches operated by clock signals comprising sequences of relatively narrow pulses substantially centered around the state transitions of the first clock signals, such that each transistor of the pair of transistors is ON when first clock signals are in a steady state, and OFF when first clock signals are changing state.
In yet another form of the chopped CMOS operational amplifier of the present invention, the modulator comprises an arrangement of transistor switches that reconfigures input-to-output connections at the clock rate. Preferably, the arrangement of transistor switches couples a first input of the modulator to a first output, and a second input of the modulator to a second output, during a first clock phase, then couples the first input to the second output and the second input to the first output during a second clock phase. The first demodulator reverses the input-to-output reconfiguration introduced by the first modulator. In one form, the first demodulator includes first and second outputs, with a current inverter coupled to one of the outputs to perform differential to single-ended conversion. The first demodulator may also comprise two capacitors per channel, with an associated network of clock-driven MOS transistor switches that enable each of the capacitors to transmit channel current in a first configuration, store channel current in a second configuration, and discharge stored channel current in a third configuration, to accomplish demodulation and differential to single-ended conversion.
In accordance with a further embodiment of the present invention, a chopped CMOS operational amplifier comprises a primary signal path including an AC amplifier preceded by a modulator and followed by a demodulator, wherein the modulator and demodulator are operated by first clock signals, and an interface network coupled between the modulator and the AC amplifier, wherein the interface network acts to open the main signal path during transitions of the first clock signals. In a preferred form, the interface network comprises a pair of transistor switches operated by clock signals comprising sequences of relatively narrow pulses substantially centered around the state transitions of the first clock signals, such that each transistor of the pair of transistors is ON when first clock signals are in a steady state, and OFF when first clock signals are changing state.
Further objects, features, and advantages of the present invention will become apparent from the following description and drawings.